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Philips Semiconductors
256 × 8-bit static low-voltage RAM with
I 2 C-bus interface
Product speci?cation
PCF8570
8
CHARACTERISTICS OF THE I 2 C-BUS
8.1
Bit transfer
The I 2 C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
SDA
SCL
data line
stable;
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
change
of data
data valid
allowed
MBA607
Fig.3 Bit transfer.
8.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
SDA
SCL
S
P
SDA
SCL
START condition
STOP condition
MBA608
Fig.4 Definition of start and stop conditions.
1999 Jan 06
5
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